SAA7376GP_M1 查看數據表（PDF） - Philips Electronics

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SAA7376GP_M1

Digital servo processor and Compact Disc decoder (CD7)

Philips Electronics 

Philips Semiconductors

Digital servo processor and Compact Disc

decoder (CD7)

Product specifications

SAA7376

7.3 Data slicer and clock regenerator

The SAA7376 has an integrated slice level comparator

which can be clocked by the crystal frequency clock, or

8 times the crystal frequency clock (if SELPLL is set HIGH

while using an 8.4672 MHz crystal, and register 4 is set

to 0xxx). The slice level is controlled by an internal current

source applied to an external capacitor under the control

of the Digital Phase-Locked Loop (DPLL).

Regeneration of the bit clock is achieved with an internal

fully digital PLL. No external components are required and

the bit clock is not output. The PLL has two registers

(8 and 9) for selecting bandwidth and equalization.

For certain applications an off-track input is necessary.

This is internally connected from the servo part (its polarity

can be changed by the foc_parm1 parameter), but may be

input via the V1 pin if selected by register C. If this flag is

HIGH, the SAA7376 will assume that its servo part is

following on the wrong track and will flag all incoming HF

data as incorrect.

7.4 Demodulator

7.4.1 FRAME SYNC PROTECTION

A double timing system is used to protect the demodulator

from erroneous sync patterns in the serial data.

The master counter is only reset if:

• A sync coincidence detected; sync pattern occurs

588 ±1 EFM clocks after the previous sync pattern

• A new sync pattern is detected within ±6 EFM clocks of

its expected position.

The sync coincidence signal is also used to generate the

PLL lock signal, which is active HIGH after 1 sync

coincidence found, and reset LOW if, during 61

consecutive frames, no sync coincidence is found. The

PLL lock signal can be accessed via the SDA or STATUS

pins selected by register 2 and 7.

Also incorporated in the demodulator is a Run Length 2

(RL2) correction circuit. Every symbol detected as RL2 will

be pushed back to RL3. To do this, the phase error of both

edges of the RL2 symbol are compared and the correction

is executed at the side with the highest error probability.

7.4.2 EFM DEMODULATION

The 14-bit EFM data and subcode words are decoded into

8-bit symbols.

1998 Feb 26

crystal

clock

HF

2.2 kΩ

input

2.2 nF

47 pF

HFIN

DQ

22 kΩ

22 nF

HFREF

1/2VDD

Iref

100 µA

VSSA

VSS

100 nF

VSSA

ISLICE

100 µA

VDD

DPLL

MGA368 - 1

Fig.5 Data slicer showing typical application components.

9

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