RT8223A/B
Discharge Mode (Soft Discharge)
When ENTRIPx is low and a transition to standby,
shutdown mode occurs, or the output under voltage fault
latch is set, the outputs discharge mode will be triggered.
During discharge mode, there is one path to discharge
the outputs capacitor residual charge. That is output
capacitor discharge to GND through an internal MOS
switch.
Shutdown Mode
The RT8223A/B SMPS1, SMPS2, VREG3 and VREG5
have independent enabling control. Drive EN, ENTRIP1,
ENTRIP2 and ENC below the precise input falling edge
trip level to place the RT8223A/B in its low power shutdown
state. The RT8223A/B consumes only 20μA of input
current while in shutdown.
Power-Up Sequencing and On/Off Controls
(ENTRIPx, ENC)
ENTRIP1 and ENTRIP2 control SMPS power-up
sequencing. When the RT8223A/B applies in the single
channel mode, ENTRIP1 or ENTRIP2 enables the
respective outputs when ENTRIPx voltage rises above
0.4V. Furthermore, the RT8223A/B applies in the dual
channel mode. ENC enables the outputs when ENC
voltage rises above 2V.
If both of ENTRIP1 and ENTRIP2 become higher than the
enable threshold voltage at a different time (without 60μs),
one can force the latter one output starts after the former
one regulates.
Output Voltage Setting (FBx)
Connect FBx directly to GND or VREG5 to enable the
fixed, SMPS output voltages (3.3V and 5V). Connect a
resistor voltage divider at the FBx between the VOUTx
and GND to adjust the respective output voltage between
2V and 5.5V (Figure 4). Choose R2 to be approximately
10kΩ, and solve for R1 using the equation :
VOUTx = VFBx
×
⎡⎢⎣1+
⎛⎜⎝
R1
R2
⎞⎟⎠⎤⎥⎦
where VFBx is 2V (typ.).
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VREG5 connects to VOUT1 through an internal switch
only when VOUT1 is above the VREG5 automatic switch
threshold (4.66V). VREG3 connects to VOUT2 through
an internal switch only when VOUT2 is above the VREG3
automatic switch threshold (3V). This is the most effective
way when the fixed output voltages are used. Once VREGx
is supplied from VOUTx, the internal linear regulator turns
off. This reduces internal power dissipation and improves
efficiency when the VREGx is powered with a high input
voltage.
VIN
UGATEx
PHASEx
LGATEx
VOUTx
FBx
PGND
GND
VOUTx
R1
R2
Figure 4. Setting VOUTx with a Resistor-Divider
Output Inductor Selection
The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as shown as
follows :
L=
TON × (VIN − VOUTx )
LIR × ILOAD(MAX)
where LIR is the ratio of the peak to peak ripple current to
the average inductor current.
Find a low loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and can work well at 200kHz. The core must
be large enough not to saturate at the peak inductor current
(IPEAK) :
IPEAK = ILOAD(MAX) + [(LIR / 2) x ILOAD(MAX)]
This inductor ripple current also impacts transient-response
performance, especially at low VIN − VOUTx differences.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter
capacitors by a sudden load step. The peak amplitude of
the output transient VSAG is also a function of the output
transient. The VSAG also features a function of the
DS8223A/B-04 April 2011