RT8015BGSP 查看數據表（PDF） - Richtek Technology
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RT8015BGSP Datasheet PDF : 16 Pages
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RT8015B
Current Limit
RT8015B has cycle by cycle current limiting control. The
current limit circuit employs a “peak” current sensing
algorithm. If the magnitude of the current sense signal is
above the current limit threshold, the controller will turn
off high side MOSFET and turn on low side MOSFET.
Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage protection. When the output voltage is less than
25% of its set voltage threshold, the under voltage
protection circuit will be triggered to terminate switching
operation and the controller will be latched unless VDD
POR is detected again. During soft-start, the UVP will be
blanked until soft-start finish.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT8015B, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For SOP-8
(Exposed Pad) packages, the thermal resistance, θJA, is
75°C/W on a standard JEDEC 51-7 four-layer thermal test
board. For WDFN-10L 3x3 packages, the thermal
resistance, θJA, is 70°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formulas :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. For the RT8015B packages, the derating
curves in Figure 4 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
Four-Layer PCB
WDFN-10L 3x3
SOP-8 (Exposed Pad)
25
50
75
100
125
Ambient Temperature (°C)
Figure 4. Derating Curves for RT8015B Package
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8015B.
` A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
` Connect the terminal of the input capacitor(s), CIN, as
close as possible to the PVDD pin. This capacitor
provides the AC current into the internal power
MOSFETs.
` LX node is with high frequency voltage swing and should
be kept within small area. Keep all sensitive small-signal
nodes away from the LX node to prevent stray capacitive
noise pick-up.
` Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of powercomponents. You can connect the copper areas
to any DC net (PVDD, VDD, VOUT, PGND, GND, or any
other DC rail in your system).
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DS8015B-04 March 2011
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