RT8005PQV 查看數據表（PDF） - Richtek Technology

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RT8005PQV

1A, 2MHz, High-Efficiency Synchronous Buck PWM Converter

Richtek Technology 

RT8005

Output Capacitor Selection

The capacitor’ s ESR determines the output ripple voltage VIN

and the initial voltage drop following a high slew-rate

2, 3

RT8005

PVDD

LX

1

L1

VOUT

R3

transient’ s edge. Typically, if the ESR requirement is

4 VDD

6

R1

FB

satisfied, the capacitance is adequate to filtering. The

output ripple voltage can be calculated as :

R5

C2

C3

5 EN

8 GND

COMP 7

PGND 9, 10

R2

R4

C1

∆VOUT = ∆IC (ESR +

1

)

8 x COUT x fOSC

VIN

C4

Where fOSC = operating frequency, COUT = output

capacitance and ∆IC = ∆IL = ripple current in the inductor.

The ceramic capacitor with low ESR value provides the

low output ripple and low size profile. Connect a

2.2µF/4.7µF ceramic capacitor at output terminal for good

performance and place the input and output capacitors as

close as possible to the device.

Figure 1

Layout Considerations

Follow the PCB layout guidelines for optimal performance

of RT8005.

1. For the main current paths as indicated in bold lines in

Figure 1, keep their traces short and wide.

2. Put the input capacitor as close as possible to the device

pins (PVDD and PGND).

3. LX node is with high frequency voltage swing and should

be kept small area. Keep analog components away from

LX node to prevent stray capacitive noise pick-up.

4. Connect feedback network behind the output capacitors.

Keep the loop area small. Place the feedback components

near the RT8005.

5.Connect all analog grounds to a command node and

then connect the command node to the power ground

behind the output capacitors.

6. An example of 2-layer PCB layout is shown in Figure 2

to Figure 3 for reference.

Figure 2. Top Layer

Figure 3. Bottom Layer

www.richtek.com

10

DS8005-08 August 2007

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