PMK35EP 查看數據表（PDF） - NXP Semiconductors.
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PMK35EP Datasheet PDF : 12 Pages
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NXP Semiconductors
PMK35EP
P-channel TrenchMOS extremely low level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
S
source
S
source
S
source
G
gate
D
drain
D
drain
D
drain
D
drain
3. Ordering information
Simplified outline
8
5
1
4
SOT96-1 (SO8)
Graphic symbol
D
G
S
001aaa025
Table 3. Ordering information
Type number
Package
Name
PMK35EP
SO8
4. Limiting values
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDS
VDGR
VGS
ID
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
25 °C ≤ Tj ≤ 150 °C
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
Tsp = 25 °C; VGS = -10 V; see Figure 1;
see Figure 3
Tsp = 100 °C; VGS = -10 V; see Figure 1
IDM
peak drain current
Tsp = 25 °C; tp ≤ 10 µs; pulsed;
see Figure 3
Ptot
total power dissipation
Tstg
storage temperature
Tj
junction temperature
Source-drain diode
Tsp = 25 °C; see Figure 2
IS
source current
Tsp = 25 °C
ISM
peak source current Tsp = 25 °C; tp ≤ 10 µs; pulsed
Min Typ Max Unit
-
-
-30 V
-
-
-30 V
-25 -
25 V
-
-
-14.9 A
-
-
-7
A
-
-
-28.8 A
-
-
-55 -
-55 -
6.9 W
150 °C
150 °C
-
-
-5.8 A
-
-
-23 A
PMK35EP
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 29 April 2010
© NXP B.V. 2010. All rights reserved.
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