FB2033BB 查看數據表（PDF） - Philips Electronics

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FB2033BB

8-bit latched/registered/pass-thru Futurebus+ universal interface transceiver

Philips Electronics 

Philips Semiconductors

8-bit latched/registered/pass-thru

Futurebus+ universal interface transceiver

Product specification

FB2033

AC ELECTRICAL CHARACTERISTICS (Continued)

B PORT LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

Tamb = +25°C, VCC = 5V,

CD = 30pF, RU = 9Ω

MIN TYP MAX

Tamb = 0 to 70°C,

VCC = 5V±10%,

CD = 30pF, RU = 9Ω

MIN

MAX

UNIT

tPLH

Propagation delay (thru mode)

tPHL

AIn to Bn

Waveform 1, 2

1.2

2.9

4.3

1.0

2.9

4.4

1.0

1.0

4.8

4.6

ns

tPLH

Propagation delay (transparent latch)

tPHL

AIn to Bn

Waveform 1, 2

1.4

3.1

4.5

1.0

3.3

4.8

1.0

1.0

5.1

5.1

ns

tPLH

Propagation delay

tPHL

LCAB to Bn

Waveform 1, 2

2.7

4.4

5.7

2.2

5.1

6.6

2.4

2.0

6.4

7.1

ns

tPLH

Propagation delay

tPHL

SABn to Bn

Waveform 1, 2

1.8

3.6

5.0

1.0

3.3

4.9

1.4

1.0

5.7

5.2

ns

tPZH

Enable/disable time

tPZL

OEB0 or OEB1 to Bn

Waveform 1, 2

1.4

3.0

4.5

1.0

3.1

5.0

1.0

1.0

5.0

5.6

ns

∆V/∆t

Output transition rate, Bn Port

20% to 80%, 80% to 20%

Test Circuit and

Waveforms

0.4

1.2

V/ns

tSK(o) Output to output skew, B port 1

Waveform 3

0.8

1.5

2.0

ns

tSK(p)

Pulse skew 2

 tPHL – tPLH  MAX

Waveform 2

0.3

1.5

ns

SYMBOL

PARAMETER

TEST CONDITION

RU = 16.5Ω

RU = 16.5Ω

UNIT

tPLH

Propagation delay (thru mode)

tPHL

AIn to Bn

Waveform 1, 2

1.2

3.0

4.4

1.0

3.0

4.5

1.0

1.0

4.9

4.7

ns

tPLH

Propagation delay (transparent latch)

tPHL

AIn to Bn

Waveform 1, 2

1.4

3.2

4.6

1.0

3.4

4.9

1.0

1.0

5.2

5.2

ns

tPLH

Propagation delay

tPHL

LCAB to Bn

Waveform 1, 2

2.7

4.5

5.8

2.2

5.2

6.7

2.4

2.0

6.5

7.2

ns

tPLH

Propagation delay

tPHL

SABn to Bn

Waveform 1, 2

1.8

3.7

5.1

1.0

3.4

5.0

1.4

1.0

5.8

5.3

ns

tPZH

Enable/disable time

tPZL

OEB0 or OEB1 to Bn

Waveform 1, 2

1.4

3.1

4.6

1.0

3.2

5.1

1.0

1.0

5.1

5.7

ns

∆V/∆t

Output transition rate, Bn Port

20% to 80%, 80% to 20%

Test Circuit and

Waveforms

0.2

0.6

V/ns

tSK(o)

tSK(p)

Output to output skew, B port 1

Pulse skew 2

 tPHL – tPLH  MAX

Waveform 3

Waveform 2

0.5

1.0

0.3

1.0

1.5

ns

1.5

ns

NOTES:

1.  tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or

HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).

2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal

duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).

1995 May 25

8

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