Timing Diagrams (Continued)
WRITE ENABLE CYCLE (WEN)
PRE
PE
tCS
CS
SK
1 0 0 A5 A4
A1 A0
DI
Start Opcode
Address
Bit Bits(2)
Bits(6)
High - Z
DO
93CS46:
Address bits pattern -> 1-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE DISABLE CYCLE (WDS)
PRE ;;;;;;;;;;;;;;;;;;;;;;;;;;;
PE ;;;;;;;;;;;;;;;;;;;;;;;;;;;
tCS
CS
SK
1 0 0 A5 A4
A1 A0
DI
Start Opcode
Address
Bit Bits(2)
Bits(6)
High - Z
DO
93CS46:
Address bits pattern -> 0-0-x-x-x-x; (x -> Don't Care, can be 0 or 1)
WRITE CYCLE (WRITE)
PRE
PE
tCS
CS
SK
1 0 1 A5
DI
Start Opcode
Bit Bits(2)
DO
93CS46:
Address bits pattern -> User defined
Data bits pattern -> User defined
A4
A1 A0 D15 D14
D1 D0
Address
Bits(6)
High - Z
Data
Bits(16)
tWP
Ready
Busy
NM93CS46 Rev. F.2
10
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