NM24W17UTLVM8 查看數據表（PDF） - Fairchild Semiconductor

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NM24W17UTLVM8

16K-Bit Serial EEPROM 2-Wire Bus Interface

Fairchild Semiconductor 

Write Cycle Timing (Figure 1)

SCL

SDA

8th BIT

ACK

Note:

WORD n

tWR

STOP

START

CONDITION

CONDITION

The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.

Data Validity (Figure 2)

DS800010-10

SCL

SDA

DATA STABLE DATA

CHANGE

Start and Stop Definition (Figure 3)

SCL

SDA

START

CONDITION

Acknowledge Response from Receiver (Figure 4)

SCL FROM

MASTER

DATA OUTPUT

FROM

TRANSMITTER

DATA OUTPUT

FROM

RECEIVER

1

START

DS800010-11

STOP

CONDITION

DS800010-12

8

9

ACKNOWLEDGE

DS800010-13

8

NM24C16U/17U Rev. B.1

www.fairchildsemi.com

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