NB6L239 查看數據表（PDF） - ON Semiconductor

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NB6L239

2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider

ON Semiconductor 

NB6L239

Application Information

The NB6L239 is a high−speed, low skew clock divider

with two divider circuits, each having selectable clock

divide ratios; B1/2/4/8 and B2/4/8/16. Both divider

circuits drive a pair of differential LVPECL outputs. The

internal dividers are synchronous to each other. Therefore,

the common output edges are precisely aligned.

The NB6L239 clock inputs can be driven by a variety of

differential signal level technologies including LVDS,

LVPECL, HSTL, or CML. The differential clock input

buffer employs a pair of internal 50 W termination resistors

in a 100 W center−tapped configuration and accessible via

the VT pin. This feature provides transmission line

termination on−chip, at the receiver end, eliminating

external components. The VBBAC reference output can be

used to rebias capacitor−coupled differential or

single−ended input CLOCK signals. For the

capacitor−coupled CLK and/or CLK inputs, VBBAC should

be connected to the VT pin and bypassed to ground with a

0.01 mF capacitor. Inputs CLK and CLK must be signal

driven or auto oscillation may result.

The common enable (EN) is synchronous so that the

internal divider flip−flops will only be enabled/disabled

when the internal clock is in the LOW state. This avoids any

chance of generating a runt pulse on the internal clock when

the device is enabled/disabled, as can happen with an

asynchronous control. The internal enable flip−flop is

clocked on the falling edge of the input clock. Therefore, all

associated specification limits are referenced to the negative

edge of the clock input.

MR

CLK

Q (÷1)

Q (÷2)

Q (÷4)

Q (÷8)

Q (÷16)

CLK

MR

Figure 4. Timing Diagram

tRR

tRR

Q (÷n)

Figure 5. Master Reset Timing Diagram

NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK.

Internal Clock

Disabled

Internal Clock

Enabled

CLK

Q (÷n)

EN

Figure 6. Output Enable Timing Diagrams

The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal

divider flip−flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge

of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela-

tionships.

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