NB2304AI2DG 查看數據表（PDF） - ON Semiconductor

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NB2304AI2DG

3.3 V Zero Delay Clock Buffer

ON Semiconductor 

NB2304A

FBK

REF

CLKA1

PLL

CLKA2

B2

Extra Divider (−2)

CLKB1

Figure 1. Basic Block Diagram

(see Figures 11 and 12 for device specific Block Diagrams)

CLKB2

Table 1. CONFIGURATIONS (x = C for Commercial; I for Industrial)

Device

Feedback From

Bank A Frequency

NB2304Ax1

Bank A or Bank B

Reference

NB2304Ax1H

Bank A or Bank B

Reference

NB2304Ax2

Bank A

Reference

NB2304Ax2

Bank B

2 X Reference

Bank B Frequency

Reference

Reference

Reference B2

Reference

REF 1

CLKA1 2

CLKA2 3

GND 4

NB2304A

8 FBK

7 VDD

6 CLKB2

5 CLKB1

Figure 2. Pin Configuration

Table 2. PIN DESCRIPTION

Pin # Pin Name

Description

1 REF (Note 1) Input reference frequency, 5 V

tolerant input.

2 CLKA1 (Note 2) Buffered clock output, Bank A.

3 CLKA2 (Note 2) Buffered clock output, Bank A.

4

GND

Ground.

5 CLKB1 (Note 2) Buffered clock output, Bank B.

6 CLKB2 (Note 2) Buffered clock output, Bank B.

7

VDD

3.3 V supply.

8

FBK

PLL feedback input.

1. Weak pulldown.

2. Weak pulldown on all outputs.

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