PRELIMINARY
CY7C4808V25
CY7C4806V25
CY7C4804V25
Table 1. Endian/Bus Matching Configuration[29]
Each character (“A”, “B”,..., “H”) represents 10-bit data
BE/FWFT Size 1A Size 2A Port A Size 1B Size 2B
Port B
bit#79 bit#0
0
1
0
x20
0
0
x80
Write to FIFO
AB
CD
EF
GH
Read from FIFO GH EF CD AB
0
1
x40
Read from FIFO
CDAB
GHEF
1
0
x20
Read from FIFO
AB
CD
EF
GH
1
1
x10
Read from FIFO
B
A
D
C
F
E
H
G
1
1
x10
0
0
x80
Write to FIFO
A
B
C
D
E
F
G
H
Read from FIFO HGFEDCBA
0
1
x40
Read from FIFO
DCBA
HGFE
1
0
x20
Read from FIFO
BA
DC
FE
HG
26