CY7C4808V25-166 查看數據表（PDF） - Cypress Semiconductor

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CY7C4808V25-166

2.5V 4K/16K/64K x 80 Unidirectional Synchronous FIFO w/Bus Matching

Cypress Semiconductor 

PRELIMINARY

CY7C4808V25

CY7C4806V25

CY7C4804V25

Table 1. Endian/Bus Matching Configuration[29]

Each character (“A”, “B”,..., “H”) represents 10-bit data

BE/FWFT Size 1A Size 2A Port A Size 1B Size 2B

Port B

bit#79 bit#0

1

0

0

x80

0

0

x80

Write to FIFO ABCDEFGH

Read from FIFO ABCDEFGH

0

1

x40

Read from FIFO

ABCD

EFGH

1

0

x20

Read from FIFO

AB

CD

EF

GH

1

1

x10

Read from FIFO

A

B

C

D

E

F

G

H

0

1

x40

0

0

x80

Write to FIFO

ABCD

EFGH

Read from FIFO ABCDEFGH

0

1

x40

Read from FIFO

ABCD

EFGH

1

0

x20

Read from FIFO

AB

CD

EF

GH

1

1

x10

Read from FIFO

A

B

C

D

E

F

G

H

Note:

29. BE is selected at Master Reset; SIZE1A, SIZE2A, SIZE1B AND SIZE2B must be static throughout device operation.

22

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