CY7C4806V25-200BBC 查看數據表（PDF） - Cypress Semiconductor

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CY7C4806V25-200BBC

2.5V 4K/16K/64K x 80 Unidirectional Synchronous FIFO w/Bus Matching

Cypress Semiconductor 

PRELIMINARY

CY7C4808V25

CY7C4806V25

CY7C4804V25

Switching Waveforms (continued)

Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset

(CY Standard and FWFT Modes) [8]

CLKA

MRS

RT/SPM

FS1/SEN,

FS0/SD

FF/IR

ENA

tSPMS

tSPMH

tFSS

tFSH

A0−79

tWFF

tENS

tENH

tDS

tDH

AF Offset (Y)

AE Offset (X) First Word

into FIFO

Serial Programming of the Almost-Full Flag and Almost-Empty Flag

[9]

Offset Values (CY Standard and FWFT Modes)

CLKA

MR

RT/SPM

FF/IR

FS1/SEN

[10]

FS0/SD

tSPMS tSPMH

tFSS

tSPH

tFSS tFSH

tSENS

tSENH

tSDS

tSDH

AF Offset (Y) MSB

tSENS tSENH

tSDS

tSDH

AE Offset (X) LSB

tWFF

Notes:

8. CSA = LOW. It is not necessary to program offset register on consecutive clock cycles.

9. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.

10. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X).

11

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