MT8941BP 查看數據表（PDF） - Zarlink Semiconductor Inc
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MT8941BP Datasheet PDF : 27 Pages
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MT8941B
Data Sheet
Crystal Clock
(16.384 MHz)
MT8941B
MS0
MS1
MS2
MS3
F0i
C12i
ENCV
C8Kb
C16i
ENC4o
ENC2o
VDD
C4b
C2o
F0b
Yo
VSS RST
MT8980/81
MH89790B
C2i
F0i
E8Ko
DSTi
DSTo
CSTi0
CSTi1
CSTo
OUTA
OUTB
RxT
RxR
TRANSMIT
RECEIVE
ST-BUS
SWITCH
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
Mode of Operation for the MT8941B
C
R VDD
DPLL #1 - NOT USED
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
Figure 12 - Synchronization at the Slave End of the CEPT Digital Transmission Link
Figures 11 and 12 show how the MT8941B can be used to synchronize the ST-BUS to the CEPT transmission link
at the master and slave ends.
Generation of ST-BUS Timing Signals
The MT8941B can source the properly formatted ST-BUS timing and control signals with no external inputs except
the crystal clock. This can be used as the standard timing source for ST-BUS systems or any other system with
similar clock requirements.
Figure 13 shows two such applications using DPLL #2. In one case, the MT8941B is in FREE-RUN mode with an
oscillator input of 16.384 MHz. In the other case, it is in NORMAL mode with the C8Kb input tied to VDD. For these
applications, DPLL #2 does not make any corrections and therefore, the output signals are free from jitter. DPLL #1
is completely free.
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