MT9042C 查看數據表（PDF） - Mitel Networks
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MT9042C Datasheet PDF : 28 Pages
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Advance Information
MT9042C
Pin Description
Pin # Name
Description (see notes 1 to 5)
16
C8o Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.
17
C16o Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation at 16.384Mb/
s.
19
GTi Guard Time (Schmitt Input). This input is used by the MT9042B state machine in both
Manual and Automatic modes. The signal at this pin affects the state changes between
Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and
Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o.
See Tables 4 and 5.
20
GTo Guard Time (CMOS Output). The LOS1 input is gated by the rising edge of F8o, buffered
and output on GTo. This pin is typically used to drive the GTi input through an RC circuit.
21
LOS2 Secondary Reference Loss (TTL Input). This input is normally connected to the loss of
signal (LOS) output signal of a Line Interface Unit (LIU). When high, the SEC reference
signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs control the MT9042B
state machine when operating in Automatic Control. The logic level at this input is gated in
by the rising edge of F8o.
22
LOS1 Primary Reference Loss (TTL Input). Typically, external equipment applies a logic high to
this input when the PRI reference signal is lost or invalid. The logic level at this input is gated
in by the rising edge of F8o. See LOS2 description.
23
MS2 Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1, determines the
device’s mode (Automatic or Manual) and state (Normal, Holdover or Freerun) of operation.
The logic level at this input is gated in by the rising edge of F8o. See Table 3.
24
MS1 Mode/Control Select 1 (TTL Input). The logic level at this input is gated in by the rising
edge of F8o. See pin description for MS1.
25
RSEL Reference Source Select (TTL Input). In Manual Control, a logic low selects the PRI
(primary) reference source as the input reference signal and a logic high selects the SEC
(secondary) input. In Automatic Control, this pin must be at logic low. The logic level at this
input is gated in by the rising edge of F8o. See Table 2.
26
FS2 Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects which of three
possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input to the PRI and SEC
inputs. See Table 1.
27
FS1 Frequency Select 1 (TTL Input). See pin description for FS2.
28
RST Reset (Schmitt Input). A logic low at this input resets the MT9042B. To ensure proper
operation, the device must be reset after changes to the method of control, reference signal
frequency changes and power-up. The RST pin should be held low for a minimum of 300ns.
While the RST pin is low, all frame and clock outputs are at logic high. Following a reset, the
input reference source and output clocks and frame pulses are phase aligned as shown in
Figure 19.
Notes:
1. All inputs are CMOS with either TTL compatible logic levels, CMOS compatible logic levels or Schmitt trigger compatible logic levels
as indicated in the Pin Description.
2. All outputs are CMOS with CMOS compatible logic levels.
3. See DC Electrical Characteristics for static logic threshold values.
4. See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for dynamic logic threshold values.
5. Unless otherwise stated, all unused inputs should be connected to logic high or logic low and all unused outputs should be left open
circuit.
3
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