24FC65-SM 查看數據表（PDF） - Microchip Technology
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24FC65-SM Datasheet PDF : 14 Pages
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3.6 Device Addressing
A control byte is the first byte received following the
START from the master device. The control byte
consists of a four bit control code, for the 24FC65 this is
set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device to
select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte (R/W)
defines the operation to be performed. When set to a
one a read operation is selected, when set to a zero a
write operation is selected. The next two bytes received
define the address of the first data byte (Figure 4-1).
Because only A12..A0 are used, the upper three
address bits must be zeros. The most significant bit of
the most significant byte is transferred first. Following
the START, the 24FC65 monitors the SDA bus checking
the device type identifier being transmitted. Upon
receiving a 1010 code and appropriate device select
bits, the slave device (24FC65) outputs an acknowledge
signal on the SDA line. Depending upon the state of the
R/W bit, the 24FC65 will select a read or write operation.
Operation
Control
Code
Device Select R/W
Read
Write
1010
1010
Device Address 1
Device Address 0
FIGURE 3-2: CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W A
1
0
1
0
A2 A1 A0
X = Don’t care
24FC65
4.0 WRITE OPERATION
4.1 Byte Write
Following the START from the master, the control code
(four bits), the device select (three bits), and the R/W bit
which is a logic low is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver (24FC65) that a byte with a word address will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmitted
by the master is the high-order byte of the word address
and will be written into the address pointer of the
24FC65. The next byte is the least significant address
byte. After receiving another acknowledge signal from
the 24FC65 the master device will transmit the data
word to be written into the addressed memory location.
The 24FC65 acknowledges again and the master
generates a STOP. This initiates the internal write cycle,
and during this time the 24FC65 will not generate
acknowledge signals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24FC65 in the same way as
in a byte write. But instead of generating a STOP the
master transmits up to eight pages of eight data bytes
each (64 bytes total) which are temporarily stored in the
on-chip page cache of the 24FC65. They will be written
from the cache into the EEPROM array after the master
has transmitted a STOP. After the receipt of each word,
the six lower order address pointer bits are internally
incremented by one. The higher order seven bits of the
word address remain constant. If the master should
transmit more than eight bytes prior to generating the
STOP (writing across a page boundary), the address
counter (lower three bits) will roll over and the pointer will
be incremented to point to the next line in the cache. This
can continue to occur up to eight times or until the cache
is full, at which time a STOP should be generated by the
master. If a STOP is not received, the cache pointer will
roll over to the first line (byte 0) of the cache, and any
further data received will overwrite previously captured
data. The STOP can be sent at any time during the
transfer. As with the byte write operation, once the STOP
is received an internal write cycle will begin. The 64 byte
cache will continue to capture data until a STOP occurs
or the operation is aborted (Figure 4-2).
FIGURE 4-1: BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
S
T CONTROL
A
BYTE
R
T
S
WORD
ADDRESS (1)
000
WORD
ADDRESS (0)
S
T
DATA
O
P
P
BUS ACTIVITY
A
A
A
A
C
C
C
C
K
K
K
K
2004 Microchip Technology Inc.
DS21125E-page 5
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