ADVANCE
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
512K x 16 SRAM COMBO MEMORY
BLOCK DIAGRAM
F_WE#
F_OE#
F_CE#
F_RP#
A19–A20
A0–A18
S_CE1#
S_CE2
S_OE#
S_WE#
F_VCC
F_VPP
FLASH
Bank a
4,096K x 16
Bank b
SRAM
512K x 16
S_VCC
F_WP#
F_VSS
VCCQ
DQ0–DQ15
S_VSS
S_UB#
S_LB#
F_RST#
F_CE#
F_WE#
F_OE#
DQ0-DQ15
Data Input
Buffer
CSM
WSM
I/O Logic
FLASH FUNCTIONAL BLOCK DIAGRAM
Data
Register
Program/
Erase
Pump Voltage
Generators
X DEC
Y/Z DEC
PR Lock
Query/OTP
Bank 1 Blocks
Y/Z Gating/Sensing
PR Lock
Query
OTP
Manufacturer’s ID
Device ID
Block Lock
RCR
ID Reg.
Status
Reg.
DQ0–DQ15
Output
Multiplexer
Output
Buffer
A0–A21
Address
Input
Buffer
Address
CNT/WSM
Address Latch
Address
Multiplexer
Y/Z DEC
X DEC
Y/Z Gating/Sensing
Bank 2 Blocks
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
4
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©2002, Micron Technology, Inc.