MPC9772 查看數據表（PDF） - Motorola => Freescale
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MPC9772 Datasheet PDF : 16 Pages
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MPC9772
Table 10. AC Characteristics (VCC = 3.3V ± 5%, TA = –40° to +85°C)1 2 (Continued)
Symbol
Characteristics
Max
Unit
Condition
Min
Typ
TA = 0°C TA = –40°C
to +70°C to +85°C
tJIT(∅)
I/O Phase Jitter RMS (1 σ)12
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
11
ps (VCO=400 MHz)
86
ps
13
ps
88
ps
16
ps
19
ps
21
ps
22
ps
27
ps
30
ps
BW
PLL closed loop bandwidth13
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
1.20 –
3.50
0.70 –
2.50
0.50 –
1.80
0.45 –
1.20
0.30 –
1.00
0.25 –
0.70
0.20 –
0.55
0.17 –
0.40
0.12 –
0.30
0.11 –
0.28
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
tLOCK
Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50Ω to VTT.
2. In bypass mode, the MPC9772 divides the input reference clock.
3. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF= fVCO ÷ (M ⋅ VCO_SEL).
4. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio:
fXTAL(min, max) = fVCO(min, max) ÷ (M ⋅ VCO_SEL) and 10 MHz ≤ fXTAL ≤ 25 MHz.
5. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% – DCREF, MIN.
6. The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(∅), tPW,MIN, DC and fMAX can only be
guaranteed if tR, tF are within the specified range.
7. Static phase offset depends on the reference frequency. t(∅) [s] = t(∅) [°] ÷ (fREF ⋅ 360°).
8. Excluding QSYNC output. See application section for part-to-part skew calculation.
9. Output duty cycle is DC = (0.5 ± 200 ps ⋅ fOUT) ⋅ 100%. E.g. the DC range at fOUT = 100 MHz is 48%<DC<52%. T = output period.
10. Cycle jitter is valid for all outputs in the same divider configuration. See application section for more details.
11. Period jitter is valid for all outputs in the same divider configuration. See application section for more details.
12. I/O jitter is valid for a VCO frequency of 400 MHz. See application section for I/O jitter vs. VCO frequency.
13. –3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
7
MOTOROLA
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