MPC9331AC 查看數據表（PDF） - Motorola => Freescale
零件编号
产品描述 (功能)
生产厂家
MPC9331AC Datasheet PDF : 12 Pages
| |||
Table 1. Pin Configuration
Pin
CCLK
PCLK, PCLK
FB_IN
FB_SEL
I/O
Input
Input
Input
Input
Type
Function
LVCMOS PLL reference clock signal
LVPECL Differential PECL reference clock signal
LVCMOS PLL feedback signal input, connect to an output
LVCMOS Feedback select
REF_SEL
PWR_DN
FSELA
FSELB
FSELC
PLL_EN
Input
Input
Input
Input
Input
Input
LVCMOS Reference clock select
LVCMOS Output frequency and power down select
LVCMOS Frequency divider select for bank A outputs
LVCMOS Frequency divider select for bank B outputs
LVCMOS Frequency divider select for bank C outputs
LVCMOS PLL enable/disable
CLK_STOP0-1
Input LVCMOS Clock output enable/disable
OE/MR
Input LVCMOS Output enable/disable (high-impedance tristate) and device reset
QA0-1, QB0-1, QC0-1 Output LVCMOS Clock outputs
GND
Supply Ground Negative power supply (GND)
VCC_PLL
VCC
Supply VCC
Supply VCC
PLL positive power supply (analog power supply). It is recommended to use external RC filter for
the analog power supply pin VCC_PLL. Please see applications section for details.
Positive power supply for I/O and core. All VCC pins must be connected to the positive power
supply for correct operation
Table 2. Function Table
Control
Default
0
1
REF_SEL
0
PCLK is the PLL reference clock
CCLK is the PLL reference clock
FB_SEL
1
Internal PLL feedback of 8. fVCO = 8 * fref
External feedback. Zero-delay operation
enabled for CCLK or PCLK as reference
clock
PLL_EN
1
Test mode with PLL disabled. The reference clock is substituted Normal operation mode with PLL enabled.
for the internal VCO output. MPC9331 is fully static and no
minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
PWR_DN
1
VCO ÷ 1 (High output frequency range)
VCO ÷ 2 (Low output frequency range)
FSELA
0
Output divider ÷ 2
Output divider ÷ 4
FSELB
0
Output divider ÷ 2
Output divider ÷ 4
FSELC
0
Output divider ÷ 4
Output divider ÷ 6
OE/MR
1
Outputs disabled (high-impedance state) and reset of the
Outputs enabled (active)
device. During reset in external feedback configuration, the PLL
feedback loop is open. The VCO is tied to its lowest frequency.
The MPC9331 requires reset after any loss of PLL lock. Loss of
PLL lock may occur when the external feedback path is
interrupted. The length of the reset pulse should be greater than
one reference clock cycle (CCLK or PCLK). Reset does not
affect PLL lock in internal feedback configuration.
CLK_STOP[0:1] 11
See Table 3
PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 8 through Table 10 for supported frequency ranges and output to input frequency ratios.
Advanced Clock Drivers Devices
Freescale Semiconductor
MPC9331
3
Share Link: 