
Truth Table
(Each Flip-Flop)
Inputs
Outputs
Clear Clock
D
Q
L
X
X
L
H
n
H
H
H
n
L
L
H
L
X
Q0
H HIGH Level (Steady State)
L LOW Level (Steady State)
X Don’t Care
n Transition from LOW-to-HIGH level
Q0 The level of Q before the indicated steady state input conditions were
established
Logic Diagram
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