MH32S64PHB-8 查看數據表（PDF） - MITSUBISHI ELECTRIC

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MH32S64PHB-8

214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH32S64PHB -7,-8,-10

214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM

DQM CONTROL

DQMB0-7 is a dual function signal defined as the data mask for writes and the output

disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7

to write mask latency is 0.

During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z

latency is 2.

DQM Function

CK

Command

Write

READ

DQMB0-7

DQ

D0

D2 D3

Q0 Q1

Q3

masked by DQM=H

disabled by DQM=H

MIT-DS-0301-0.0

MITSUBISHI

ELECTRIC

( 30 / 55 )

11/Jan. /1999

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