MH32S64PHB-8 查看數據表（PDF） - MITSUBISHI ELECTRIC

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MH32S64PHB-8

214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH32S64PHB -7,-8,-10

214683648-BIT (3354432- WORD BY 64-BIT)SynchronousDRAM

[ BURST WRITE ]

A burst write operation is enabled by setting A9=0 at MRS.A burst write stats in

the same cycle as a write command set.(The latency of data input is 0.) The

burst length can be set to 1,2,4,8,and full-page,like burst read operations.

tRCD

CK

Command

ACT

READ

Address

X

Y

DQ

Q0

BL=1

DQ

Q0 Q1

BL=2

DQ

Q0 Q1 Q2 Q3

BL=4

DQ

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

BL=8

DQ

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

Qm Q0 Q1 BL=FP

m=1023

Full Page counter rolls over

and continues to count.

[ SINGLE WRITE ]

A single write operation is enabled by setting A9=1 at MRS.In a single write

operation,data is written only to the column address specified by the write

command set cycle without regard to the burst length setting.(The latency of data

input is 0.)

CK

Command

Address

DQ

ACT

READ

tRCD

X

Y

Q0

MIT-DS-0301-0.0

MITSUBISHI

ELECTRIC

( 21 / 55 )

11/Jan. /1999

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