MH16S64AMA-12 查看數據表（PDF） - MITSUBISHI ELECTRIC

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MH16S64AMA-12

1073741824-BIT (16777216 - WORD BY 64-BIT) SynchronousDRAM

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

[ Write Interrupted by Precharge ]

Burst write operation can be interrupted by precharge of the same bank. Random

column access is allowed. Because the write recovery time(tWR) is required between

the last input data and the next PRE, 3rd data should be masked with DQMB0-7

shown as below.

Write Interrupted by Precharge (BL=4)

CK

Command

A0-9,11

Write

Yi

PRE

tWR

ACT

tRP

Xb

A10

0

0

Xb

BA0,1

0

0

0

DQMB0-7

DQ

Dai0 Dai1

This data should be masked to satisfy tWR requirement.

[ Write Interrupted by Burst Terminate ]

Burst terminate command can terminate burst write operation. In this case, the write

recovery time is not required and the bank remains active. The figure below shows

the case 3 words of data are written. Random column access is allowed. WRITE to

TERM interval is minimum 1 CK.

CK

Command

A0-9,11

A10

BA0,1

DQMB0-7

DQ

Write Interrupted by Burst Terminate (BL=4)

Write

Yi

0

0

TERM

Dai0 Dai1 Dai2

MIT-DS-0127-0.0

MITSUBISHI

ELECTRIC

( 24 / 52 )

4. Mar.1997

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