MCM67Q709AZP10R 查看數據表（PDF） - Motorola => Freescale

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MCM67Q709AZP10R

128K x 9 Bit Separate I/O Synchronous Fast Static RAM

Motorola => Freescale 

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V

Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns

Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V

Output Load . . . . . . . . . . . . . . . . . Figure 1a Unless Otherwise Noted

READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)

MCM67Q709A–10

Parameter

Symbol

Min

Max

Unit Notes

Cycle Time

Clock Access Time

Clock Low Pulse Width

Clock High Pulse Width

Clock High to Data Output Invalid

Clock High to Data Output High–Z

Setup Times:

tKHKH

10

tKHQV

—

tKLKH

4

tKHKL

4

tKHQX

2

tKHQZ

—

A

tAVKH

2

W

tWVKH

E

tEVKH

G

tGVKH

D0 – D8

tDVKH

—

ns

1

5

ns

2

—

ns

—

ns

—

ns

5

ns

3

—

ns

4

Hold Times:

A

tKHAX

1

W

tKHWX

E

tKHEX

G

tKHGX

D0 – D8

tKHDX

—

ns

4

NOTES:

1. All read and write cycles are referenced from K.

2. Valid data from Clock High will be the data stored at the address or the last valid read cycle.

3. Measured at ± 200 mV from steady state. Tested per High–Z Test Load (See Figure 1b).

4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising

edges of clock (K) while the device is selected.

OUTPUT

Z0 = 50 Ω

(a)

RL = 50 Ω

VL = 1.5 V

Figure 1. Test Loads

OUTPUT

255 Ω

+5V

480 Ω

5 pF

(b)

MCM67Q709A

4

MOTOROLA FAST SRAM

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