MCM6227BJ25R2 查看數據表（PDF） - Motorola => Freescale

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MCM6227BJ25R2

1M x 1 Bit Static Random Access Memory

Motorola => Freescale 

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

6227B–15

6227B–17

6227B–20

6227B–25

6227B–35

Parameter

Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes

Write Cycle Time

tAVAV

15

—

17

—

20

—

25

—

35

—

ns

3

Address Setup Time

tAVWL

0

—

0

—

0

—

0

—

0

—

ns

Address Valid to End of tAVWH 12

—

14

—

15

—

17

—

20

—

ns

Write

Write Pulse Width

Data Valid to End of

Write

tWLWH, 12

—

14

—

15

—

17

—

20

—

ns

tWLEH

tDVWH

7

—

8

—

8

—

10

—

11

—

ns

Data Hold TIme

Write Low to Data

High–Z

tWHDX

0

—

0

—

0

—

0

—

0

—

ns

tWLQZ —

6

—

7

—

7

—

8

—

8

ns 4, 5, 6

Write High to Output

Active

tWHQX

5

—

5

—

5

—

5

—

5

—

ns 4, 5, 6

Write Recovery Time

tWHAX

0

—

0

—

0

—

0

—

0

—

ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con-

tention conditions during read and write cycles.

3. All timings are referenced from the last valid address to the first transitioning address.

4. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b.

5. This parameter is sampled and not 100% tested.

6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

WRITE CYCLE 1 (W Controlled See Notes 1 and 2)

tAVAV

tAVWH

tAVWL

HIGH–Z

tWLQZ

tWLWH

tWLEH

tDVWH

DATA VALID

HIGH–Z

tWHAX

tWHDX

tWHQX

MOTOROLA FAST SRAM

MCM6227B

5

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