Micrel
BLLOOGCICKDDIIAAGGRRAAMM(1)
SY10E136
SY100E136
BITS 2 – 4
Q5
D5
Q2 – Q5
D2 – D4
Q1
D1
Q0
D0
E136 Universal Up/Down Counter Logic Diagram
NOTE:
1. This diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved
internally without incurring a full gate delay.
2