MC74HC125ADTR2G 查看數據表（PDF） - ON Semiconductor
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MC74HC125ADTR2G Datasheet PDF : 9 Pages
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MC74HC125A,
MC74HC126A
Quad 3−State Noninverting
Buffers
High−Performance Silicon−Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to
the LS125 and LS126. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be
used with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low (HC125A) or active−high (HC126A).
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7A Requirements
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• Pb−Free Packages are Available
14
1
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
N SUFFIX
CASE 646
1
MC74HC12xAN
AWLYYWWG
14
1
14
SOIC−14
D SUFFIX
CASE 751A
1
HC12xAG
AWLYWW
14
1
TSSOP−14
DT SUFFIX
CASE 948G
14
HC
12xA
ALYWG
G
1
14
14
1
SOEIAJ−14
F SUFFIX
CASE 965
74HC12xA
ALYWG
1
A
=
Assembly Location
L, WL =
Wafer Lot
Y, YY =
Year
W, WW =
Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
October, 2006 − Rev. 11
Publication Order Number:
MC74HC125A/D
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