M68HC117L6MP4 查看數據表（PDF） - Freescale Semiconductor

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M68HC117L6MP4

ROM-based high-performance microcontrollers

Freescale Semiconductor 

Freescale Semiconductor, Inc.

tions. Shift and rotate instructions operate with and through the carry bit to facilitate

multiple-word shift operations.

3.1.6.2 Overflow (V)

The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V

bit is cleared.

3.1.6.3 Zero (Z)

The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is

zero. Otherwise, the Z bit is cleared. Compare instructions do an internal implied sub-

traction and the condition codes, including Z, reflect the results of that subtraction. A

few operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags.

For these operations, only = and - conditions can be determined.

3.1.6.4 Negative (N)

The N bit is set if the result of an arithmetic, logic, or data manipulation operation is

negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative if its

most significant bit (MSB) is a one. A quick way to test whether the contents of a mem-

ory location has the MSB set is to load it into an accumulator and then check the status

of the N bit.

3.1.6.5 Interrupt Mask (I)

The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable in-

terrupt sources. While the I bit is set, interrupts can become pending, but the operation

of the CPU continues uninterrupted until the I bit is cleared. After any reset, the I bit is

set by default and can only be cleared by a software instruction. When an interrupt is

recognized, the I bit is set after the registers are stacked, but before the interrupt vector

is fetched. After the interrupt has been serviced, a return from interrupt instruction is

normally executed, restoring the registers to the values that were present before the

interrupt occurred. Normally, the I bit is zero after a return from interrupt is executed.

Although the I bit can be cleared within an interrupt service routine, “nesting” interrupts

in this way should only be done when there is a clear understanding of latency and of

the arbitration mechanism. Refer to SECTION 5 RESETS AND INTERRUPTS.

3.1.6.6 Half Carry (H)

The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit

during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half carry is

used during BCD operations.

3.1.6.7 X Interrupt Mask (X)

The XIRQ mask (X) bit disables interrupts from the pin. After any reset, X is set by de-

fault and must be cleared by a software instruction. When an interrupt is recognized,

the X and I bits are set after the registers are stacked, but before the interrupt vector

is fetched. After the interrupt has been serviced, an RTI instruction is normally execut-

ed, causing the registers to be restored to the values that were present before the in-

CENTRAL PROCESSING UNIT

TECHNICAL DATA

3-5

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