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MC44603AP

Enhanced Mixed Frequency Mode GreenLine™ PWM Controller:

ON Semiconductor 

MC44603A

threshold level established by the Error Amplifier output

(Pin 13). Thus, the error signal controls the peak inductor

current on a cycle−by−cycle basis. The Current Sense

Comparator PWM Latch ensures that only a single pulse

appears at the Source Output during the appropriate

oscillator cycle.

The inductor current is converted to a voltage by inserting

the ground referenced sense resistor RS in series with the

power switch Q1.

This voltage is monitored by the Current Sense Input

(Pin 7) and compared to a level derived from the Error Amp

output. The peak inductor current under normal operating

conditions is controlled by the voltage at Pin 13 where:

Ipk

[

V(Pin 13) – 1.4 V

3 RS

The Current Sense Comparator threshold is internally

clamped to 1.0 V. Therefore, the maximum peak switch

current is:

Ipk(max)

[

1.0 V

RS

UVLO

VOSC prot

VDemag Out

Thermal

Protection

S

RQ

R

PWM

Latch

Current Sense

Comparator

VC

14

R2

3

D

1N5819

Current

Substrate Sense

7

C

Vin

Q1

R3

R

RS

Figure 34. Output Totem Pole

Series gate resistor, R2, will dampen any high frequency

oscillations caused by the MOSFET input capacitance and

any series wiring inductance in the gate−source circuit.

Diode D is required if the negative current into the output

drive pin exceeds 15 mA.

Oscillator

The oscillator is a very accurate sawtooth generator that

can work either in free mode or in synchronization mode. In

this second mode, the oscillator stops in the low state and

waits for a demagnetization or a synchronization pulse to

start a new charging cycle.

• The Sawtooth Generation:

In the steady state, the oscillator voltage varies between

about 1.6 V and 3.6 V.

The sawtooth is obtained by charging and discharging an

external capacitor CT (Pin 10), using two distinct current

sources = Icharge and Idischarge. In fact, CT is permanently

connected to the charging current source (0.4 Iref) and so,

the discharge current source has to be higher than the

charge current to be able to decrease the CT voltage (refer

to Figure 36).

This condition is performed, its value being (2.0 Iref) in

normal working and (0.4 Iref + 0.5 IF Stby in standby mode).

10

CT

Vref

0.4 Iref

1.0 V

1.6 V

3.6 V

CVOS prot

VOSC prot

COSC Low

COSC High

CT < 1.6 V

Discharge

RQ

Disch

S

RQ

LOSC

S

COSC Regul

VOSC

Synchro

VDemag

Out

01

10

IRegul

IDischarge

Figure 35. Oscillator

Vref

ICharge

0.4 Iref

10

1.6 V

COSC Regul

0 1 0: Discharge Phase

1: Charge Phase

CT

IDischarge

IRegul

Figure 36. Simplified Block Oscillator

Two comparators are used to generate the sawtooth. They

compare the CT voltage to the oscillator valley (1.6 V) and

peak reference (3.6 V) values. A latch (Ldisch) memorizes

the oscillator state.

In addition to the charge and discharge cycles, a third state

can exist. This phase can be produced when, at the end of the

discharge phase, the oscillator has to wait for a

synchronization or demagnetization pulse before restarting.

During this delay, the CT voltage must remain equal to the

oscillator valley value (]1.6 V). So, a third regulated

current source IRegul controlled by COSC Regul, is connected

to CT in order to perfectly compensate the (0.4 Iref) current

source that permanently supplies CT.

The maximum duty cycle is 80%. Indeed, the on−time is

allowed only during the oscillator capacitor charge.

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