MC33989D 查看數據表（PDF） - Motorola => Freescale

零件编号

产品描述 (功能)

生产厂家

MC33989D

System Basis Chip With High Speed CAN Transceiver

Motorola => Freescale 

MC33989

DEVICE DESCRIPTION

3.1

CAN error detection and wake up

3.1.1 Dominant State Time-out

This protection is based on the fact that all CAN signals can not have more than five bits in a row with the same state. In case

of a condition the Tx pin is stuck at 0v, the transceiver would hold the bus in dominant state making it impossible to the others

CAN modules to use the bus. The protection acts releasing the bus when a dominant signal with more than 140uS is present in

the Tx signal. After entering the fault condition the driver is disabled. To clear this disabled state the CAN transceiver needs to

have its input going to recessive state.

3.1.2 Internal Error output flags

There are internal error flags to signals when an error occurs. The flags are enabled when one of the below condition

happens:

• Thermal protection activated.

• Over Current detection in CANL or CANH pins.

• Time-out condition for dominant state.

3.1.3 Standby mode & Wake-up via CAN bus feature

The HSCAN interface enters in a low consumption mode when the CAN standby mode s enable (stand-by mode). In this

mode the HSCAN module will have a 100uA consumption via internal 5V.

When in stand-by mode the transmitter and the normal receiver are disable, the only part of circuit which remains working is

the wake up module. This module has a receiver to check the bus lines and according to its activity generate a wake up output

signal. The conditions for the wake is meet when there are 3 valid pulses in a row. A valid signal must have a pulse width

bigger than 0.5uS and no more than 0.5mS.

diagram to be inserted

Figure 4. Wake up block diagram

The block diagram shows how the wake up signal is generated. First the CAN signal is detected by a low consumption

receiver (WU receiver). The signal pass through a pulse width filter to validate the signal.

The signal pass through a pulse width filter in order to select or discard the input signal according to its width. If the pulse

width is greater than 500uS the signal pass to the “pulse ok” node with 0.5uS of delay. If the width of pulse is less than 0.5uS no

signal appears on “pulse ok” node and a pulse appears in “Narrow pulse” node. A narrow pulse will reset the counter.

The time-out generator block act as a retriggerable mono stable, when the first signal appears it causes a low signal output

disabling the counter reset and beginning to count, if the next CAN signal do not occurs within 0.5mS the time out node will reset

the counter. After the counter reach the number 3 the Wake up output is latched until the standby signal be disabled. The wake

up output do not takes the CAN out of stand-by mode. In order to do this an external circuit should change the standby input

signal.

System Basis Chip With High Speed CAN Transceiver

9

Share Link: