2.5MHz/1.5MHz Step-Down Converters
with 60mΩ Bypass in TDFN for CDMA PA Power
Table 1. Suggested Inductors
MANUFACTURER
SERIES
Coilcraft
Cooper
LP03310
SD3110
SD3112
FDK
Panasonic
Sumida
Taiyo Yuden
TOKO
MIPF2520D
ELC3FN
CDRH2D09
CDRH2D11
CB2016
CBC2016
CB2518
CBC2518
NR3010
MDT2520-CR
D2812C
INDUCTANCE
(µH)
1.5
3.3
1.5
1.5
3.3
1.5
3.3
2.2
1.5
3.3
2.2
2.2
2.2
2.2
1.5
3.3
2.2
1.5
1.3
ESR
(Ω)
0.10
0.16
0.11
0.10
0.17
0.07
0.10
0.12
0.05
0.10
0.13
0.20
0.09
0.13
0.08
0.14
0.08
0.11
0.17
CURRENT
RATING (mA)
1400
950
970
1090
840
1500
1200
1000
680
450
510
750
510
890
1200
840
700
900
730
DIMENSIONS
3.3 x 3.3 x 1.0 = 11mm3
3.1 x 3.1 x 1.05 = 10mm3
3.1 x 3.1 x 1.2 = 12mm3
2.5 x 2.0 x 1.0 = 5mm3
3.2 x 3.2 x 1.2 = 12mm3
3.2 x 3.2 x 1.2 = 12mm3
2.0 x 1.25 x 1.45 = 3.6mm3
2.0 x 1.6 x 1.8 = 5.8mm3
2.5 x 1.8 x 2.0 = 9mm3
3.2 x 3.2 x 1.2 = 12mm3
2.5 x 2.0 x 1.0 = 5mm3
2.8 x 2.8 x 1.2 = 9.4mm3
PCB Layout
Checklist
High switching frequencies and relatively large peak cur-
L1 = FDK MIPF2520 SERIES
rents make the PCB layout a very important part of
1.5μH FOR MAX8581
3.3μH FOR MAX8582
design. Good design minimizes excessive EMI on the
C1, C2 = TAIYO YUDEN JMK105BJ225MV-B
L1
feedback paths and voltage gradients in the ground
GND
plane, both of which can result in instability or regulation
errors. Connect the input capacitor close to IN and GND.
IN
C1
Connect the inductor and output capacitor as close to
C2
OUT
the IC as possible and keep their traces short, direct,
and wide. Keep noisy traces, such as the LX node, as
SHDN
GND
short as possible. Connect GND to the exposed paddle
HP
directly under the IC. Figure 2 illustrates an example
PCB layout and routing scheme.
REFIN
Chip Information
PROCESS: BiCMOS
Figure 2. Example PCB Layout and Routing Scheme
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