2.5MHz/1.5MHz Step-Down Converters
with 60mΩ Bypass in TDFN for CDMA PA Power
Pin Description
PIN
NAME
1
GND
Ground
FUNCTION
2, 3
IN
Supply Voltage Input. 2.7V to 5.5V. Bypass with a 2.2µF ceramic capacitor as close as possible to IN
and GND.
4
SHDN
Active-Low Shutdown Input. Connect to IN or logic-high for normal operation. Connect to GND or
logic-low for shutdown mode.
5
HP
High-Power Mode Set Input. Drive HP high to invoke bypass mode. Bypass mode connects IN
directly to OUT with the internal bypass MOSFET.
6
REFIN
DAC-Controlled Input. Output regulates to 2 x VREFIN for the MAX8581 and MAX8582. Dual-mode
threshold at 0.465 VIN enables bypass mode.
7
IC
Internally Connected. Connect to ground.
8, 9
OUT
Output Voltage Connection for Bypass Mode. Internally connected to IN using the internal bypass
MOSFET during bypass mode. Connects to the internal feedback network.
10
LX
Inductor Connection. Connect inductor to the drains of the internal p-channel and n-channel
MOSFETs. Connects to the internal feedback network.
—
EP
Exposed Paddle. Connect to GND.
Detailed Description
The MAX8581/MAX8582 step-down converters deliver
over 600mA to dynamically power the PA in CDMA
handsets. The hysteretic PWM control scheme switches
with nearly fixed frequency at 1.5MHz (MAX8582) to
2.5MHz (MAX8581), allowing efficiency and tiny external
components. A 60mΩ bypass mode connects the PA
directly to the battery during high-power transmission.
Control Scheme
A hysteretic PWM control scheme ensures high effi-
ciency, fast switching, fast transient response, low out-
put ripple, and physically tiny external components.
This control scheme is simple: When the output voltage
is below the regulation voltage, the error comparator
begins a switching cycle by turning on the high-side
switch. This switch remains on until the minimum on-
time expires and the output voltage is in regulation or
the current-limit threshold is exceeded. Once off, the
high-side switch remains off until the minimum off-time
expires and the output voltage falls out of regulation.
During this period, the low-side synchronous rectifier
turns on and remains on until the high-side switch turns
on again. The internal synchronous rectifier eliminates
the need for an external Schottky diode.
Voltage-Positioning Load Regulation
The MAX8581/MAX8582 utilize a unique feedback net-
work. By taking feedback from the LX node, the usual
phase lag due to the output capacitor is removed, mak-
ing the loop exceedingly stable and allowing the use of
very small ceramic output capacitors. This configura-
tion yields load regulation equal to half the inductor’s
series resistance multiplied by the load current. This
voltage-positioning load regulation greatly reduces
overshoot during load transients or when changing
VOUT from one voltage to another. However, when cal-
culating REFIN voltage, the load regulation should be
considered. Because inductor resistance is typically
well specified and the typical PA is a resistive load, the
VREFIN to VOUT gain is slightly less than 2V/V for the
MAX8581/MAX8582.
Bypass Mode
During high-power transmission, the bypass mode’s
low on-resistance provides low dropout, long battery
life, and high output-current capability. Bypass mode
connects IN directly to OUT with the internal 60mΩ
(typ) bypass FET, while the step-down converter is
forced into 100% duty-cycle operation to slightly lower
total on-resistance to less than 60mΩ (typ).
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