256-Tap SOT-PoT,
Low-Drift Digital Potentiometers in SOT23
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V, VH = VDD, VL = 0, TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted. Parameters are mea-
sured at TA = +25°C. Values over full temperature range are guaranteed by design.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
VIH
VCC = 5V
VIL
VCC = 5V
VIH
VCC = 3V
VIL
VCC = 3V
0.7 ✕ VDD
0.7 ✕ VDD
V
0.3 ✕ VDD
V
V
0.3 ✕ VDD
V
±1.0
µA
Input Capacitance
5.0
pF
TIMING CHARACTERISTICS (Voltage Divider Mode)
Wiper Settling Time
MAX5400 (to 50% of final value, from code 0
to code 128)
300
tIL
ns
MAX5401 (to 50% of final value, from code 0
to code 128)
600
TIMING CHARACTERISTICS (Digital) (Note 5)
SCLK Clock Period
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup
Time
tCP
tCH
tCL
tCSS
100
ns
40
ns
40
ns
40
ns
SCLK Rise to CS Rise Hold Time
DIN Setup Time
DIN Hold Time
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
tCSH
tDS
tDH
tCS0
tCS1
tCSW
0
ns
40
ns
0
ns
10
ns
40
ns
100
ns
Note 1: Linearity is defined in terms of the H to L code-dependent resistance.
Note 2: The DNL and INL are measured with the potentiometer configured as a voltage-divider with H = VDD and L = 0. The wiper
terminal is unloaded and measured with an ideal voltmeter.
Note 3: The DNL and INL are measured with the potentiometer configured as a variable resistor. H is unconnected and L = 0. The
wiper terminal is driven with a source current of 80µA for the 50kΩ configuration and 40µA for the 100kΩ configuration.
Note 4: The wiper resistance is measured assuming the source currents given in Note 2.
Note 5: Digital timing is guaranteed by design.
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