MAX5380LEUK 查看數據表（PDF） - Maxim Integrated

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MAX5380LEUK

Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23

Maxim Integrated 

Low-Cost, Low-Power, 8-Bit DACs with

2-Wire Serial Interface in SOT23

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10kΩ; CL = 50pF,

TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

POWER REQUIREMENTS

MAX5380

2.7

3.6

Supply Voltage

VDD MAX5381

MAX5382

4.5

5.5

V

2.7

5.5

Supply Current

IDD

No load, all digital inputs at 0 or VDD, code = 255

Shutdown mode

150

230

µA

1

DIGITAL INPUTS (SCL, SDA)

Input Low Voltage

VIL

0.3 x VDD V

Input High Voltage

VIH

0.7 x VDD

V

Input Hysteresis

VHYS

Input Capacitance

CIN

Input Leakage Current

IIN

Pulse Width of Spike Suppressed tSP

DIGITAL OUTPUT (SDA, open drain)

Output Low Voltage

VOL

Output Fall Time

tOF

(Note 7)

ISINK = 3mA

ISINK = 6mA

VIH(MIN) to VIL(MAX),

bus capacitance =

10pF to 400pF

ISINK = 3mA

ISINK = 6mA

0.05 x VDD

V

10

pF

±10

µA

0

50

ns

0.4

V

0.6

250

ns

250

TIMING CHARACTERISTICS

(Figure 3; VDD = +2.7V to +3.6V (MAX5380), VDD = +4.5V to +5.5V (MAX5381), VDD = +2.7V to +5.5V (MAX5382); RL = 10kΩ;

CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) (Note 7)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

SCL Clock Frequency

fSCL

0

400 kHz

Bus Free Time Between a

STOP and a START Condition

tBUF

1.3

µs

Hold Time Repeated for a

START Condition

tHD:STA

0.6

µs

Low Period of the SCL Clock

High Period of the SCL Clock

Setup Time for a Repeated

START Condition

tLOW

tHIGH

tSU:STA

1.3

µs

0.6

µs

0.6

µs

Data Hold Time

Data Setup Time

tHD:DAT

tSU:DAT

0

0.9

µs

100

ns

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