MAX17000ETG(2011) 查看數據表（PDF） - Maxim Integrated

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MAX17000ETG
(Rev.:2011)

Complete DDR2 and DDR3 Memory Power-Management Solution

Maxim Integrated 

Complete DDR2 and DDR3 Memory

Power-Management Solution

+5V

R3

100kΩ

R2

100kΩ

+5V

CVDD

1µF

PGND

5V VCC

R1

10Ω

CVCC

1µF

AGND

SLP_S3#

ON/OFF

VCC

1

OVP

2

PGOOD1

3

PGOOD2

19

VDD

23

VCC

RTON

14

TON

BST 17

15

DH

CBST

0.1µF

LX 16

18

DL

NL

PGND1 20

CSH 13

CSL 12

VIN

7V TO 20V

CIN

NH

PGND

L1

RSENSE

D1

PGND

VDDQ

+1.8V OR 1.5V

COUT

PGND

21 AGND MAX17000

FB 11

4

STDBY

24

SHDN

22 SKIP

10

REFIN

VTTI 9

PGND2 7

VTT

VTTS

VTTR

PGND

8

5

6

EP

AGND

PGND

RFBA

RFBB

AGND

FB OPTIONS:

1. CONNECT FB TO 5V FOR FIXED +1.8V.

2. CONNECT FB TO GND FOR FIXED +1.5V.

3. USE FB RESISTOR-DIVIDER FOR ADJUSTABLE

OUTPUT VOLTAGES.

CVTTI

+1V TO + 2.5V

CVTT

VTT = VDDQ/2

CVTTR

0.33µF

AGND

VTTR = VDDQ/2

Figure 1. MAX17000 Standard Application Circuit

Detailed Description

The MAX17000 complete DDR solution comprises a

step-down controller, a source/sink LDO regulator, and a

reference buffer. Maxim’s proprietary Quick-PWM pulse-

width modulator in the MAX17000 is specifically

designed for handling fast load steps while maintaining a

relatively constant operating frequency and inductor

operating point over a wide range of input voltages. The

Quick-PWM architecture circumvents the poor load-tran-

sient timing problems of fixed-frequency current-mode

PWMs, while also avoiding the problems caused by

widely varying switching frequencies in conventional con-

stant-on-time and constant-off-time PWM schemes.

Figure 1 is the MAX17000 standard application circuit

and Figure 2 is the MAX17000 functional diagram.

The MAX17000 includes a ±2A source/sink LDO regu-

lator for the memory termination rail. The source/sink

regulator features a dead band that either sources or

sinks, ideal for the fast-changing short-period loads

presenting in memory termination applications. This

feature also reduces the VTT output capacitance

requirement down to 1µF, though load-transient

response can still require higher capacitance values

between 10µF and 20µF.

The reference buffer sources and sinks ±3mA, generating

a reference rail for use in the memory controller and

memory devices.

16 ______________________________________________________________________________________

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