MAX503CAG 查看數據表（PDF） - Maxim Integrated

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MAX503CAG

5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC

Maxim Integrated 

5V, Low-Power, Parallel-Input,

Voltage-Output, 10-Bit DAC

REFOUT

REFIN

ROFS

33µF

2N7002

REFGND

AGND

DGND

CLR

CLR

A0

A1

CS

WR

LDAC

2.048V

REFERENCE

POWER-ON

RESET

MAX503

CONTROL

LOGIC

NBL

INPUT

LATCH

DAC

10-BIT DAC LATCH

NBM

INPUT

LATCH

NBH

INPUT

LATCH

D6/S0 D8/D0

D2 D4

D7/S1

D9/D1 D3 D5

RFB

VOUT

VDD

+5V

VSS

Figure 3. Low-Current Shutdown Mode

Table 2. Input Latch Addressing

CLR CS WR LDAC A0 A1 DATA UPDATED

LXX

X

X X Reset DAC latches

HHX

H

X X No operation

HXH

H

X X No operation

HLL

H

H H NBH (D6–D9)

HLL

H

H L NBM (D2–D5)

HLL

H

L

H

NBL (S0 = 0, S1 = 0,

D0, D1)

HHH

L

X X Update DAC only

NBL and NBM (S0, S1,

HLL

X

L L D0–D5), DAC not

updated

HLL

L

H H NBH and update DAC

An additional 110µA of supply current can be saved

when the internal reference is not used by connecting

REFGND to VDD. A low on-resistance N-channel FET,

such as the 2N7002, can be used to turn off the internal

reference to create a shutdown mode with minimum

current drain (Figure 3). When CLR is high, the transis-

tor pulls REFGND to AGND and the reference and DAC

operate normally. When CLR goes low, REFGND is

pulled up to VDD and the reference is shut down. At the

same time, CLR resets the DAC register to all 0s, and

the op-amp output goes to 0V for unity-gain and

G = 2 modes. This reduces the total single-supply

operating current from 250µA (400µA max) to typically

40µA in shutdown mode.

10 ______________________________________________________________________________________

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