M74HC40102 查看數據表（PDF） - STMicroelectronics

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M74HC40102

8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER

STMicroelectronics 

M74HC40102

TYPICAL APPLICATIONS

PROGRAMMABLE DIVIDE-BY-N COUNTER

fOUT = fIN / (N+1)

Timing Chart when N = "3"

(J0, J1 = VCC , J2-J7 = GND

HC40102 ... 1/2 to 1/100 are dividable

PARALLEL CARRY CASCADING

* At synchronous cascade connection, huzzerd occurs at C0 output after its second stage when digit place changes, due to delay arrival.

Therefore, take gate from HC32 or the like, not from C0 output at the rear stage directly

PROGRAMMABLE TIMER

The above formula does not take into account the phase of clock input. Therefore, the real pulse width is the distance between the above

formula-1/fIN ~ The above formula

8/16

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