LTC2624(2004) 查看數據表（PDF） - Linear Technology

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LTC2624
(Rev.:2004)

Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP

Linear Technology 

U

OPERATIO

LTC2604/LTC2614/LTC2624

INPUT WORD (LTC2604)

COMMAND

ADDRESS

DATA (16 BITS)

C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB

LSB

2604 TBL01

INPUT WORD (LTC2614)

COMMAND

ADDRESS

DATA (14 BITS + 2 DON’T-CARE BITS)

C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

MSB

LSB

2604 TBL02

INPUT WORD (LTC2624)

COMMAND

ADDRESS

DATA (12 BITS + 4 DON’T-CARE BITS)

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

MSB

LSB

2604 TBL03

Daisy-Chain Operation

The serial output of the shift register appears at the SDO

pin. Data transferred to the device from the SDI input is

delayed 32 SCK rising edges before being output at the

next SCK falling edge.

The SDO output can be used to facilitate control of multiple

serial devices from a single 3-wire serial port (i.e., SCK,

SDI and CS/LD). Such a “daisy chain” series is configured

by connecting SDO of each upstream device to SDI of the

next device in the chain. The shift registers of the devices

are thus connected in series, effectively forming a single

input shift register which extends through the entire chain.

Because of this, the devices can be addressed and con-

trolled individually by simply concatenating their input

words; the first instruction addresses the last device in the

chain and so forth. The SCK and CS/LD signals are

common to all devices in the series.

In use, CS/LD is first taken low. Then the concatenated

input data is transferred to the chain, using SDI of the first

device as the data input. When the data transfer is com-

plete, CS/LD is taken high, completing the instruction

sequence for all devices simultaneously. A single device

can be controlled by using the no-operation command

(1111) for the other devices in the chain.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than four outputs are needed. When in power-down, the

buffer amplifiers, bias circuits and reference inputs are

disabled, and draw essentially zero current. The DAC

outputs are put into a high-impedance state, and the

output pins are passively pulled to ground through indi-

vidual 90k resistors. Input- and DAC-register contents are

not disturbed during power-down.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in combina-

tion with the appropriate DAC address, (n). The 16-bit data

word is ignored. The supply current is reduced by approxi-

mately 1/4 for each DAC powered down. The effective

resistance at REF x (pins 3, 6, 12 and 15) are at high-

impedance input (typically > 1GΩ) when the correspond-

ing DACs are powered down.

Normal operation can be resumed by executing any com-

mand which includes a DAC update, as shown in Table 1.

The selected DAC is powered up as its voltage output is

updated. When a DAC which is in a powered-down state is

powered up and updated, normal settling is delayed. If less

than four DACs are in a powered-down state prior to the

update command, the power-up delay time is 5µs. If on the

2604f

11

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