LC72710 查看數據表（PDF） - SANYO -> Panasonic

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LC72710

Mobile FM Multiplex Broadcast (DARC) Receiver IC with On-Chip VICS Decoder

SANYO -> Panasonic 

LC72710W, 72710LW

Block Number Register

Address Register R/W Initial value

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

02H

BLNO

R

—

BLN7

BLN6

BLN5

BLN4

BLN3

BLN2

BLN1

BLN0

Indicates the block number or the parity block number of the output data.

A single frame consists of data blocks numbered 0 to 189 and parity blocks numbered 0 to 81. Output following vertical

correction does not include parity block data.

The value of the block number register is undefined if VEC_HALT (bit 2 in control register 1) is set to 1.

Data Update Timing for Read Registers

The data in the two read registers (the status register at address 01H and the block number register at address 02H) is

updated in the 1 ms interval between 1 ms prior to the output of the interrupt control signal (INT) and a point

immediately before the INT output.

In normal processing, when an interrupt occurs, the application will first determine the nature of the data packet that will

be output by the current interrupt signal by reading out the status register, and determine if it is necessary to read out that

data. For example, if error correction failed and the erroneous data is not required, the application should simply wait for

the next interrupt.

If the CCB interface is used, the application reads out the data from CCB address #FB, and determines the status from the

additional 16 bits of data. It then either reads out the following data or sets the CE signal low to cancel the readout.

Applications can also read out data asynchronously with respect to the interrupt signal. In this case, the application

checks the current reception status by reading out the status register and checking bit 6 (data received in the block

synchronized state) and bit 5 (data received in the frame synchronized state). In this case, using data for which bit 7 (VH)

is 0 provides superior real time characteristics.

CPU Interface Timing <Parallel Mode>

• Register Read Timing

A0 to A3

tWRDL1, tWRDL2

tCYRD

CS

RD

RDY

tSARD

DATn

tHARD

tDRDY

tWRDY

tRDH

Valid

output

* tHARD stipulates the earliest timing for A0 to A3 and CS.

No. 6166-15/33

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