SAA7346 查看數據表（PDF） - Philips Electronics

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SAA7346

Shock absorbing RAM addresser

Philips Electronics 

Philips Semiconductors

Shock absorbing RAM addresser

Preliminary specification

SAA7346

Read operation sequence:

• SILD is held LOW by the microcontroller.

• Status information is clocked from the internal status

register on the LOW-to-HIGH clock transition of SICL.

• SICL and SILD are pulled HIGH by the microcontroller

to indicate that communications have finished.

DRAM interface

The SAA7346 may be connected to all standard 80 ns,

1M × 4 bit or 256K × 4 bit fast page mode DRAMs. The

best performance can be expected with the 4 Mbit DRAM.

The CONFIG input selects the DRAM configuration either

HIGH 4 Mbit or LOW 1 Mbit format. The SAA7346

converts audio data from serial to parallel and stores it as

4 bits. The addresses for read or write actions are

calculated by separate read and write pointers which are

multiplexed onto a 4 bits address bus. The control signal

outputs associated with the parallel inputs/outputs are

shown in Table 5.

Table 5 Command register flag functions.

COMMAND

DESCRIPTION

WE

indicates write enable action

RAS

row address strobe

CAS

column address strobe

OE

output buffer enable for external memory

during cycle.

When the SAA7346 leaves bypass mode where all parallel

Port control lines are pulled HIGH, the device initiates a

DRAM power-up routine in accordance with the JEDEC

standard.

System clock

The system clock input, CLKIN, recommended input signal

is 16.9344 MHz. The accuracy of this clock influences the

accuracy of the I2S output, therefore the performance of

the DAC and hence audio quality. The system clock is

divided by 384 to derive the I2S output word clock, WCO

divided by 8 to derive the I2S output bit clock, SCLO.

Therefore whatever clock jitter the user introduces on the

CLKIN signal will be reflected in the WCO and SCLO

outputs.

Reset

Reset should be applied for four system clock cycles.

Reset will:

• Clear SSD

• Clear the command register but leave the bypass flag

set.

After a reset has been applied the SAA7346 will start-up in

bypass mode.

Kill interface

The kill interface can be used to deactivate the DAC. The

kill input is passed directly to the KILLOUT output when the

bypass flag in the command register is set. When the flag

is not set KILLOUT is generated by the SAA7346. It is

LOW after leaving bypass mode, a reset or a FIFO flush. It

will be LOW until the first error free word is read from the

FIFO. The kill input has no effect or function when the

bypass flag is not set.

Read cycle divide (RCD2)

The RCD2 input enables the modes of operation shown in

Table 6. When RCD2 is HIGH the DRAM-read requests

are halved allowing I2S output speeds to vary. The factor

n is called the over-speed factor.

July 1994

10

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