SAA5284 查看數據表（PDF） - Philips Electronics
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SAA5284 Datasheet PDF : 24 Pages
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Philips Semiconductors
Multimedia video data acquisition circuit
Objective specification
SAA5284
handbook, full pagewidth
A2 to A0
D7 to D0
CS1 or CS0
t1
3-state
t0
valid address
t2
valid data
t3
R/W
t4
LDS
t5
t6
DTACK
A(1)
B(2)
(1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean).
Fig.7 Motorola mode interface write cycle timing.
3-state
t7
MGK149
Table 7 Motorola-mode interface write cycle timing (12 MHz clock)
SYMBOL
DESCRIPTION
t0
minimum cycle time
t1
address set-up time before event A
t2
address hold time after event B
t3
data hold time from event B
t4
data set-up time
t5
DTACK set-up time
t6
LDS HIGH to DTACK HIGH
t7
delay between cycles
MIN.
333
0
0
0
0
−
83
83
MAX.
417
−
−
−
−
212
212
−
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
1998 Feb 05
16
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