SAA5284 查看數據表（PDF） - Philips Electronics
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SAA5284 Datasheet PDF : 24 Pages
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Philips Semiconductors
Multimedia video data acquisition circuit
Objective specification
SAA5284
handbook, full pagewidth
A2 to A0
D7 to D0
CS1 or CS0
R/W
LDS
DTACK
t1
3-state
t0
valid address
t2
valid data
t3
t4
t5
A(1)
t6
B(2)
3-state
t7
MGK148
(1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean).
Fig.6 Motorola mode interface read cycle timing.
Table 6 Motorola-mode interface read cycle timing (12 MHz clock)
SYMBOL
t0
t1
t2
t3
t4
t5
t6
t7
DESCRIPTION
minimum cycle time
address set-up time before event A
address hold time after event B
data hold time from event B
data settling time
data valid to DTACK LOW
LDS HIGH to DTACK HIGH
delay between cycles
MIN.
333
0
0
0
88
83
83
83
MAX.
833
−
−
−
712
170
212
−
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
1998 Feb 05
15
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