ISPLSI2064V-80LJ44I 查看數據表（PDF） - Lattice Semiconductor
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ISPLSI2064V-80LJ44I Datasheet PDF : 14 Pages
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Specifications ispLSI 2064V
Power Consumption
Power consumption in the ispLSI 2064V device depends Figure 3 shows the relationship between power and
on two primary factors: the speed at which the device is operating speed.
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
120
110
100
90
ispLSI 2064V
DESIGNS
80
70
0
25
50
fmax (MHz)
75
NEW 100
Notes: Configuration of Four 16-bit Counters
Typical Current at 3.3V, 25° C
OR ICC can be estimated for the ispLSI 2064V using the following equation:
F ICC(mA) = 10 + (# of PTs * 0.556) + (# of nets * Max freq * 0.0053)
Where:
E # of PTs = Number of Product Terms used in design
V # of nets = Number of Signals used in device
4 Max freq = Highest Clock Frequency to the device (in MHz)
6 The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads
0 on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
2 and the program in the device, the actual ICC should be verified.
0127/2064
SI Power-up Considerations
L When Lattice 3.3-Volt 2000V devices are used in mixed
p 5V/3.3V applications, some consideration needs to be
is given to the power-up sequence. When the I/O pins on
the 3.3V ispLSI devices are driven directly by 5V devices,
a low impedance path can exist on the 3.3V device
E between its I/O and Vcc pins when the 3.3V supply is not
present. This low impedance path can cause current to
S flow from the 5V device into the 3.3V ispLSI device. The
U maximum current occurs when the signals on the I/O pins
This latch-up condition occurs only during the power-up
sequence when the 5V supply comes up before the 3.3V
supply. The Lattice 3.3V ispLSI devices are guaranteed
to withstand 5V interface signals within the device oper-
ating Vcc range of 3.0V to 3.6V.
The recommended power-up options are as follows:
Option 1: Ensure that the 3.3V supply is powered-up and
are driven high by the 5V devices. If a large enough stable before the 5V supply is powered up.
current flows through the 3.3V I/O pins, latch-up can Option 2: Ensure that the 5V device outputs are driven to
occur and permanent device damage may result.
a high impedance or logic low state during power-up.
8
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