IS61LPS102418A-250B3 查看數據表（PDF） - Integrated Silicon Solution

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IS61LPS102418A-250B3

256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

Integrated Silicon Solution 

IS61VPS25672A, IS61LPS25672A

IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A

READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

Symbol Parameter

-250

Min. Max.

-200

Min. Max.

Unit

fMAX Clock Frequency

—

250

—

200

MHz

tKC

Cycle Time

4.0

—

5

—

ns

tKH

Clock High Time

1.7

—

2

—

ns

tKL

Clock Low Time

1.7

—

2

—

ns

tKQ

Clock Access Time

—

2.6

—

3.1

ns

tKQX(2) Clock High to Output Invalid

0.8

—

1.5

—

ns

tKQLZ(2,3) Clock High to Output Low-Z

0.8

—

1

—

ns

tKQHZ(2,3) Clock High to Output High-Z

—

2.6

—

3.0

ns

tOEQ Output Enable to Output Valid

—

2.8

—

3.1

ns

tOELZ(2,3) Output Enable to Output Low-Z

0

—

0

—

ns

tOEHZ(2,3) Output Disable to Output High-Z

—

2.6

—

3.0

ns

tAS

Address Setup Time

1.2

—

1.4

—

ns

tWS Read/Write Setup Time

1.2

—

1.4

—

ns

tCES Chip Enable Setup Time

1.2

—

1.4

—

ns

tAVS Address Advance Setup Time

1.2

—

1.4

—

ns

tDS

Data Setup Time

1.2

—

1.4

—

ns

tAH

Address Hold Time

0.3

—

0.4

—

ns

tWH

Write Hold Time

0.3

—

0.4

—

ns

tCEH Chip Enable Hold Time

0.3

—

0.4

—

ns

tAVH Address Advance Hold Time

0.3

—

0.4

—

ns

tDH

Data Hold Time

0.3

—

0.4

—

ns

tPDS ZZ High to Power Down

—

2

—

2

cyc

tPUS ZZ Low to Power Down

—

2

—

2

cyc

Note:

1. Configuration signal MODE is static and must not change during normal operation.

2. Guaranteed but not 100% tested. This parameter is periodically sampled.

3. Tested with load in Figure 2.

Integrated Silicon Solution, Inc. — 1-800-379-4774

17

Rev. N

02/12/2010

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