IN74AC651 查看數據表（PDF） - IK Semicon Co., Ltd

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IN74AC651

Octal 3-State Bus Transceivers and D Flip-Flops High-Speed Silicon-Gate CMOS

IK Semicon Co., Ltd 

IN74AC651

TIMING REQUIREMENTS (CL=50pF,Input tr=tf=3.0 ns)

Symbol

Parameter

VCC*

V

tsu

Minimum Setup Time, A or B Data Port to A- 5.0

to-B Clock or B-to-A Clock (Figure 7)

th

Minimum Hold Time, A-to-B Clock or

5.0

B-to-A Clock to A or B Data Port (Figure 7)

tw

Minimum Pulse Width, A-to-B Clock or

5.0

B-to-A Clock (Figure 7)

Guaranteed Limits

25 °C

-40°C to Unit

85°C

7.0

8.0

ns

2.5

2.5

ns

6.0

7.0

ns

TIMING DIAGRAM

Rev. 00

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