IDT82V3385(2009) 查看數據表（PDF） - Integrated Device Technology

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IDT82V3385
(Rev.:2009)

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

IDT82V3385

SYNCHRONOUS ETHERNET WAN PLL

3

FUNCTIONAL DESCRIPTION

3.1 RESET

The reset operation resets all registers and state machines to their

default value or status.

After power on, the device must be reset for normal operation.

For a complete reset, the RST pin must be asserted low for at least

50 µs. After the RST pin is pulled high, the device will still be in reset

state for 500 ms (typical). If the RST pin is held low continuously, the

device remains in reset state.

3.2 MASTER CLOCK

A nominal 12.8000 MHz clock, provided by a crystal oscillator, is

input on the OSCI pin. This clock is provided for the device as a master

clock. The master clock is used as a reference clock for all the internal

circuits. A better active edge of the master clock is selected by the

OSC_EDGE bit to improve jitter and wander performance.

In fact, an offset from the nominal frequency may input on the OSCI

pin. This offset can be compensated by setting the

NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within

±741 ppm.

The performance of the master clock should meet GR-1244-CORE,

GR-253-CORE, ITU-T G.812 and G.813 criteria.

Table 2: Related Bit / Register in Chapter 3.2

Bit

NOMINAL_FREQ_VALUE[23:0]

OSC_EDGE

Register

NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG

DIFFERENTIAL_IN_OUT_OSCI_CNFG

Address (Hex)

06, 05, 04

0A

Functional Description

18

March 23, 2009

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