IDT82V3380 查看數據表（PDF） - Integrated Device Technology

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IDT82V3380

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

IDT82V3380

SYNCHRONOUS ETHERNET WAN PLL

Table 1: Pin Description (Continued)

Name

IN5_POS

IN5_NEG

IN6_POS

IN6_NEG

IN7

IN8

IN9

IN10

IN11

IN12

IN13

IN14

FRSYNC_8K

MFRSYNC_2K

OUT1

Pin No.

40

41

42

43

48

51

52

53

54

55

56

57

30

31

88

I/O

Type

Description 1

IN5_POS / IN5_NEG: Positive / Negative Input Clock 5

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz or

I

PECL/LVDS 622.08 MHz clock is differentially input on this pair of pins. Whether the clock signal is PECL

or LVDS is automatically detected.

Single-ended input for differential input is also supported. Refer to Chapter 9.3.3.3 Single-

Ended Input for Differential Input.

IN6_POS / IN6_NEG: Positive / Negative Input Clock 6

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 156.25 MHz, 311.04 MHz or

I

PECL/LVDS 622.08 MHz clock is differentially input on this pair of pins. Whether the clock signal is PECL

or LVDS is automatically detected.

Single-ended input for differential input is also supported. Refer to Chapter 9.3.3.3 Single-

Ended Input for Differential Input.

I

pull-down

CMOS

IN7: Input Clock 7

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

I

pull-down

CMOS

IN8: Input Clock 8

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

I

pull-down

CMOS

IN9: Input Clock 9

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

I

pull-down

CMOS

IN10: Input Clock 10

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

I

pull-down

CMOS

IN11: Input Clock 11

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

In Slave operation, the frequency of the T0 selected input clock IN11 is recommended to be

6.48 MHz.

I

pull-down

CMOS

IN12: Input Clock 12

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

I

pull-down

CMOS

IN13: Input Clock 13

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

I

pull-down

CMOS

IN14: Input Clock 14

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

Output Frame Synchronization Signal

O

CMOS

FRSYNC_8K: 8 kHz Frame Sync Output

An 8 kHz signal is output on this pin.

O

CMOS

MFRSYNC_2K: 2 kHz Multiframe Sync Output

A 2 kHz signal is output on this pin.

Output Clock

OUT1: Output Clock 1

O

CMOS A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,

77.76 MHz or 155.52 MHz clock is output on this pin.

Pin Description

14

May 19, 2009

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