IDT82V3355 查看數據表（PDF） - Integrated Device Technology

零件编号

产品描述 (功能)

生产厂家

IDT82V3355

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

IDT82V3355

SYNCHRONOUS ETHERNET WAN PLL

3.3 INPUT CLOCKS & FRAME SYNC SIGNALS

Altogether 5 clocks and 3 frame sync signals are input to the device.

3.3.1 INPUT CLOCKS

The device provides 5 input clock ports.

According to the input port technology, the input ports support the fol-

lowing technologies:

• PECL/LVDS

• CMOS

According to the input clock source, the following clock sources are

supported:

• T1: Recovered clock from STM-N or OC-n

• T2: PDH network synchronization timing

• T3: External synchronization reference timing

IN1_CMOS ~ IN3_CMOS support CMOS input signal only and the

clock sources can be from T1, T2 or T3.

IN1_DIFF and IN2_DIFF support PECL/LVDS input signal and auto-

matically detect whether the signal is PECL or LVDS. The clock sources

can be from T1, T2 or T3.

For SDH and SONET networks, the default frequency is different.

SONET / SDH frequency selection is controlled by the IN_SONET_SDH

bit. During reset, the default value of the IN_SONET_SDH bit is deter-

mined by the SONET/SDH pin: high for SONET and low for SDH. After

reset, the input signal on the SONET/SDH pin takes no effect.

IDT82V3355 supports single-ended input for differential input. Refer

to Chapter 8.3.2.3 Single-Ended Input for Differential Input.

3.3.2 FRAME SYNC INPUT SIGNALS

Three 2 kHz, 4 kHz or 8 kHz frame sync signals are input on the

EX_SYNC1 to EX_SYNC3 pins respectively. They are CMOS inputs.

The input frequency should match the setting in the SYNC_FREQ[1:0]

bits.

Only one of the three frame sync input signals is used for frame sync

output signal synchronization. Refer to Chapter 3.13.2 Frame SYNC

Output Signals for details.

Table 3: Related Bit / Register in Chapter 3.3

Bit

IN_SONET_SDH

SYNC_FREQ[1:0]

Register

INPUT_MODE_CNFG

Address (Hex)

09

Functional Description

18

May 19, 2009

Share Link: