IDT82V2058(2004) 查看數據表（PDF） - Integrated Device Technology

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IDT82V2058
(Rev.:2004)

OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2058 OCTAL E1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL TEMPERATURE RANGES

TABLE - 1b. SYSTEM INTERFACE CONFIGURATION (Hardware Mode)

MCLK

clocked

clocked

H

L

TDNn

H ( 16 MCLK)

pulse

pulse

pulse

Hardware Mode

Interface

Single Rail mode 1

Dual Rail with Clock Recovery

Receive just slice the incoming data. Transmit is determined by the status of TCLKn.

Receive is power down. Transmit is determined by the status of TCLKn.

TABLE - 2. ACTIVE CLOCK EDGE AND ACTIVE LEVEL

Pin CLKE

Low

RD/RDP and CV/RDN

Clock recovery

Slicer output

RCLK

Active High Active Low

SDO

SCLK Active High

High

RCLK

Active High Active High

SCLK Active High

RECEIVER

In receive path, the line signals couple into RRINGn and RTIPn via

a transformer and are converted into RZ digital pulses by a data

slicer. Adaptation for attenuation is achieved using an integral peak

detector that sets the slicing levels. Clock and data are recovered

from the received RZ digital pulses by a digital phase-locked loop that

provides excellent jitter accommodation. After passing through the

selectable jitter attenuator, the recovered data are decoded using

HDB3 or AMI line code rules and clocked out of pin RDn in single rail

mode, or presented on RDPn/RDNn in an undecoded dual rail NRZ

format. Loss of signal, alarm indication signal, line code violations and

excessive zero are detected. These various changes in status may

be enabled to generate interrupts.

The clock recovery and data recovery mode can be selected on

per channel basis by setting the bit CRSn in e-CRS. When bit CRSn is

defaulted to ‘0’, the corresponding channel operates in data and clock

recovery mode. The recovered clock is output on pin RCLKn and re-

timed NRZ data are output on pin RDPn/RDNn in dual rail mode or on

RDn in single rail mode. When CRSn is ‘1’, dual rail with data

recovery mode is enabled in the corresponding channel and the clock

recovery function is bypassed. In this condition, the analog line signal

are converted to RZ digital bit streams on the RDPn/RDNn pins and

internally connected to an EXOR which is fed to the RCLKn output for

external clock recovery applications.

Moreover, Pulling MCLK to H level, all the receivers will enter the

dual rail with data recovery mode. In this case, e-CRS is ignored.

Peak Detector and Slicer

The slicer determines the presence and polarity of the received

pulses. In data recovery mode, the raw positive slicer output appears

on RDPn while the negative slicer output appears on RDNn. In clock

and data recovery mode, the slicer output is sent to Clock and Data

Recovery circuit for abstracting retimed data and optional decoding.

The slicer circuit has a built-in peak detector from which the slicing

threshold is derived. The slicing threshold is default to 50% (typical) of

the peak value.

Signals with an attenuation of up to 12 dB (from 2.4V) can be re-

covered accurately by the receiver. To provide immunity from impul-

sive noise, the peak detectors are held above a minimum level of

0.150 V typically, despite the received signal level.

Clock and Data Recovery

The function of Clock and Data Recovery is accomplished by

Digital Phase Locked Loop (DPLL). The DPLL is clocked 16 times of

the received clock rate, i.e. 32.768 MHz in E1 mode. The recovered

data and clock from DPLL is then sent to the selectable Jitter

Attenuator or decoder circuit for further processing.

HDB3/AMI Line Code Rule

Selectable HDB3 or AMI line coding/decoding is provided when the

device is configured in single rail mode. HDB3 rules is enabled by set-

ting bit CODE in register GCF (global control configuration) to ‘0’ or

pulling pin CODE to Low. AMI rule is enabled by setting bit CODE in

GCF to ‘1’ or pulling pin CODE to High. All the setting above are ef-

fected to eight channels.

Individual line code rule selection for each channel, if need, is

available by setting bit SINGn in e-SING to ‘1’ (to activate bit CODEn in

e-CODE) and programming bit CODEn to select line code rules in the

corresponding channel: ‘0’ for HDB3, while ‘1’ for AMI. In this case, the

value in bit CODE in GCF or pin CODE for global control is unaffected

in the corresponding channel and only affect in other channels.

In dual rail mode, the decoder/encoder are bypassed. Bit CODE in

GCF, bit CODEn in e-CODE and pin CODE are ignored.

The configuration of the Line Code Rule is summarized in Table-3.

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