IDT82V2054DAG 查看數據表（PDF） - Integrated Device Technology
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IDT82V2054DAG Datasheet PDF : 56 Pages
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IDT82V2054
QUAD E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Pin No.
Type
TQFP144 PBGA160
Description
SDI: Serial Data Input
In serial host mode, this pin input the data to the serial interface. Data on this pin is sampled on the rising
edges of SCLK.
SDI/WR/DS
I
84
SDO/RDY/ACK
O
83
O
INT
Open
82
Drain
D7/AD7
28
D6/AD6
27
D5/AD5
I/O
26
D4/AD4
25
LP3/D3/AD3
24
LP2/D2/AD2 High-Z
23
LP1/D1/AD1
22
LP0/D0/AD0
21
WR: Write Strobe (Active Low)
In parallel Intel host mode, this pin is active low during write operation. The data on D[7:0] (in non-multi-
plexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on the rising edges of WR.
J14 DS: Data Strobe (Active Low)
In parallel Motorola host mode, this pin is active low. During a write operation (R/W = 0), the data on D[7:0]
(in non-multiplexed mode) or AD[7:0] (in multiplexed mode) is sampled into the device on the rising edges
of DS. During a read operation (R/W = 1), the data is driven to D[7:0] (in non-multiplexed mode) or AD[7:0]
(in multiplexed mode) by the device on the rising edges of DS.
In parallel Motorola non-multiplexed host mode, the address information on the 5 bits of address bus
A[4:0] are latched into the device on the falling edges of DS.
NOTE: This pin is ignored in hardware control mode.
SDO: Serial Data Output
In serial host mode, the data is output on this pin. In serial write operation, SDO is always in high-Z. In
serial read operation, SDO is in high-Z only when SDI is in address/command byte. Data on pin SDO is
clocked out of the device on the falling edges of SCLK if pin CLKE is high, or on the rising edges of SCLK
if pin CLKE is low.
K14 RDY: Ready Output
In parallel Intel host mode, the high level of this pin reports to the host that bus cycle can be completed,
while low reports the host must insert wait states.
ACK: Acknowledge Output (Active Low)
In parallel Motorola host mode, the low level of this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write operation.
INT: Interrupt (Active Low)
K13 This is the open drain, active low interrupt output. Three sources may cause the interrupt. Refer to 2.19
Interrupt Handling for details.
LPn: Loopback Select 3~0
In hardware control mode, pin LPn configures the corresponding channel in different loopback mode, as
follows:
LPn
Loopback Configuration
K1
Low
Remote Loopback
J1
VDDIO/2
No loopback
J2
High
Analog Loopback
J3 Refer to 2.12 Loopback Mode for details.
J4 In hardware control mode, D4 to D7 should be tied to VDDIO/2.
H2 Dn: Data Bus 7~0
H3 In non-multiplexed host mode, these pins are the bi-directional data bus.
G2
ADn: Address/Data Bus 7~0
In multiplexed host mode, these pins are the multiplexed bi-directional address/data bus.
In serial host mode, these pins should be grounded.
Pin Description
8
September 22, 2005
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